1. Field of the Invention
The present disclosure relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
In recent years, an LSI (Large Scale Integration) technology, which is a key technology for realizing a multimedia device, has been steadily developed to attain high speed and large capacity of data transmission. Accordingly, densification of a packaging technology that becomes an interface between the LSI and an electronic device is in progress. Especially, a technology for laminating a plurality of substrates formed with elements in a direction vertical to surfaces of the substrates and connecting wiring lines three-dimensionally has attracted attention.
A resistance and a capacity (RC components) between the elements can be reduced by the lamination in a three-dimensional direction. Further, when the packaging technology at a wafer level has been developed, cost reduction is also made possible.
One of methods for realizing a three-dimensional lamination structure is a direct bonding method. In the direct bonding method, a wiring layer is provided on a substrate formed with a circuit and the two substrates are bonded so that the wiring layers face each other.
For example, in a conventional structure, a circuit element and a wiring layer are provided on a substrate in a laminated body, and the two laminated bodies are bonded. After that, a through-hole that penetrates from a rear surface side of one or both of the laminated bodies to an interface on a front surface side of the laminated body is provided so as to be in contact with a conductive pad part provided in the laminated body. By embedding a conductive material in the provided through-hole, conduction between wafers is achieved (refer to Unexamined Japanese Patent Publication No. 2012-204443, for example).
As illustrated in FIG. 8, in a semiconductor device described in Unexamined Japanese Patent Publication No. 2012-204443, first laminated body 10, in which functional element 12 and wiring layer 13 are formed on substrate 11, and second laminated body 20, in which functional element 22 and wiring layer 23 are formed on substrate 21, are bonded so that respective main surfaces face each other. Functional element 12 is covered with insulating film 15, and functional element 22 is covered with insulating film 25.
A wiring line located on a surface of first laminated body 10 and a wiring line located on a surface of second laminated body 20 are metal-bonded to each other. With this configuration, first laminated body 10 and second laminated body 20 are electrically connected.
Further, through-electrode 17 is formed in first laminated body 10 so that through-electrode 17 penetrates substrate 11 and one end of through-electrode 17 connects with the wiring line of wiring layer 13. Another end of through-electrode 17 is connected with pad electrode 18 provided on a rear surface of substrate 11 and serving as an external connection terminal.
Insulating layers 16, 26 for securing an insulation property of the substrate are formed on surfaces of substrate 11 and substrate 21, which are respectively opposite to surfaces that functional elements 12, 22 are formed on.
By using this structure, it is possible to realize the semiconductor device in which the elements are laminated in a vertical direction to main surfaces of the substrates and which is packaged at high density.